Substrate used for group iii-v nitride growth and method for preparation thereof

ABSTRACT

A substrate used for III-V-nitride growth and a manufacturing method thereof, the manufacturing method comprising the following steps: 1) providing a growth substrate, and forming on the surface of the growth substrate a buffer layer used for subsequent growth of a luminescent epitaxial structure; 2) forming a semiconductor dielectric layer on the surface of the buffer layer; 3) by means of a photolithography process, etching a plurality of semiconductor dielectric protrusions arranged at intervals on the semiconductor dielectric layer, and exposing the buffer layer between the semiconductor dielectric protrusions. This method ensures the crystal quality of the grown luminescent epitaxial structure and also raises the luminescent efficiency of a light-emitting diode. The process is simple, advantageous for reducing cost of manufacture, and suitable for use in industrial production.

BACKGROUND OF THE PRESENT INVENTION

Field of Invention

The invention relates to the field of semiconductor illumination, andparticularly relates to a substrate used for an III-V-nitride growth anda manufacturing method thereof.

Description of Related Arts

As a new highly-effective solid light source, the semiconductorillumination has advantages of long lifetime, energy saving,environmental protection and safety, etc., and the application areathereof is rapidly broadening. A core of the semiconductor illuminationis a light-emitting diode (LED), that is a PN junction structurallyformed by a III-V-compound such as GaAs (gallium arsenide), GaP (galliumphosphide), GaAsP (gallium arsenide phosphide), GaN (gallium nitride)semiconductor and the like. Therefore, the LED has an I-V characteristicof a general PN junction, i.e., forward-conductive, reverse-blocking andbreakdown characteristics. In addition, the LED has a luminescencecharacteristic under certain conditions. Under forward voltages,electrons are implanted from an N region to a P region, while holes areimplanted from the P region to the N region. A part of minority carriersentering a counterpart region are recombined with majority carriers forluminescence.

In order to improve luminous efficiency of the LED, generally, an activeregion of a quantum well is added between an n-type layer and a p-typelayer of the PN junction, a luminous wavelength of the LED depends onthe material of the quantum well and the PN junction of the LED and thewidth of the quantum well, while a GaN based III-V-nitride, comprisingInGaN, AlGaN and the like, is an optimal material for preparing avisible LED. Most LEDs are prepared by using an epitaxial growth method,with a specific structure of successively grown N-type layer, activeregion, P-type layer on a substrate. Due to the lack of a cheap GaNhomogeneous substrate, a GaN-based LED is generally grown on a foreignsubstrate, e.g., a Si, SiC or sapphirine substrate, etc., wherein thesapphirine substrate is most widely used.

It is very difficult to grow a high quality crystal material on aforeign substrate, let alone growing a device level GaN crystal materialon the sapphirine substrate, until in the earlier 1990s, Japanesedeveloped a two-step grown method to grow a device level GaN epitaxiallayer by using a metal organic compound vapor deposition (MOCVD) method.Wherein, the so-called two-step grown method is that: firstly growing aGaN or AlGaN buffer layer with a thickness of about 30 nm on a surfaceof the sapphirine substrate at a growth temperature of about 500° C.,then raising the growth temperature over 1000° C. to grow a high qualityGaN epitaxial layer. A device prepared by such method has a large amountof dislocations, while the higher the dislocation density is, the lowerluminous efficiency of the device is.

Currently, the most widely used so-called patterned sapphirine substrate(PSS) technology may reduce the dislocation density in the epitaxiallayer, improve internal quantum efficiency of the LED, as well asimprove light-extraction efficiency of the LED by diffuse scattering ofthe PPS patterns. A conventional PSS technology is to form variousmicroscopic patterns on the surface of the sapphirine by using aphotolithography process or an etching process. For example, a (0001)oriented surface of the sapphirine is formed with cone-shapedprojections of a certain periodic structure, wherein the cone-shapedprojections is still made of the sapphirine material, and there remainsa certain area of (0001) crystal plane between the cone-shapedprojections. Since there is a certain selective growth mechanism betweenthe surface of the cone-shaped projections and the (0001) crystal planebetween the cone-shaped projections, that is, during the epitaxialgrowth, the nucleation probability on the (0001) crystal plane betweenthe cone-shaped projections is larger than that on the surfaces of thecone-shaped projections, and the epitaxial layer on the cone-shapedprojection is generally formed by lateral growth, as a result, theepitaxial growth on the PSS substrate has a lateral growth effect, whichmay reduce the dislocation density in the epitaxial layer and improvethe internal quantum efficiency of the LED using the PSS substrate. Onthe other hand, the microscopic structure of the surface of the PSSsubstrate has a certain diffuse scattering effect on emitted light bythe LED, which is destructive to total reflection, and accordingly, thePSS substrate enables to improve the light-extraction efficiency of theLED. The foregoing two-step method is also available for growing a LEDepitaxial structure on a conventional PSS substrate.

The conventional PSS technology has many disadvantages. Firstly, thesapphirine has great difficulty in manufacturing no matter by using awet method or a dry method, thereby not only affecting production yieldof the conventional PPS, but also increasing manufacturing cost;secondly, since the growth selectivity is not apparent between thesurface of the cone-shaped projections of the sapphirine and the (0001)crystal plane between cone-shaped projections, the surface of thecone-shaped projection will nucleate if the area of the (0001) crystalplane between cone-shaped projections is too small, besides, since thecrystal orientation of the crystal nucleus formed on the surface of thecone-shaped projection differs from the crystal orientation of thecrystal nucleus formed on the (0001) crystal plane between cone-shapedprojections, generation of polycrystal is easily caused; thirdly, sincethe sapphirine substrate has a relative large refractive index, which isabout 1.8, even if a protrusion structure is formed on the its surface,it is not optimal for the diffuse scattering effect of the emitted lightby the LED, and the improvement of the light-extraction efficiency isalso limited.

An epitaxial lateral overgrowth (ELO) technology is to form a dielectricmask on a high quality GaN epitaxial layer with a thickness of the orderof micrometers, followed by a second epitaxial growth to obtain GaN withrelative low dislocation density. The high quality GaN epitaxial layerhas a single crystal structure and incurs high production cost.Moreover, the GaN between the dielectric pattern and the sapphirinesurface having a thickness larger than 1 micron may affect the diffusescattering effect, and the GaN with a thickness larger than 1 micron mayalso affect consistency and reproducibility of the device.

It has been reported in articles to directly form a dielectric layerpattern on the surface of the sapphirine substrate for epitaxial growth,but the growth window is very small, and thus there is no value of massproduction.

Currently, there is a technology to sputter a layer of aluminium nitride(AlN) with a certain crystal orientation on a conventional PSS, which isdifferent from the above technology and the price/performance ratio ofwhich is also lower than that of the above technology.

Therefore, it is desirable to provide a novel pattern substrate and amanufacturing method thereof to effectively improve the crystallinequality of the GaN based epitaxial layer and the LED epitaxialstructure, e.g., reducing the dislocation density, and to improvevarious performance indexes of the LED, especially the luminousefficiency of the LED.

SUMMARY OF THE PRESENT INVENTION

In view of the above disadvantages in the prior art, an object of theinvention is to provide a substrate used for III-V-nitride growth and amanufacturing method thereof, to solve the problem that the growthquality and the luminous flux of the light emitting diode are low in theprior art.

The invention provides a substrate used for III-V-nitride growth, atleast comprising:

a growth substrate;

a buffer layer used for growing a subsequent luminescent epitaxialstructure, wherein a lower surface of the buffer layer is combined witha surface of the growth substrate; and

a plurality of semiconductor dielectric protrusions arranged atintervals on an upper surface of the buffer layer, bottom surfaces ofthe protrusions are combined with the upper surface of the buffer layer,and the buffer layer is exposed between protrusions.

The invention further provides a manufacturing method of the substrateused for III-V-nitride growth, at least comprising the following stepsof:

1) providing a growth substrate, and forming on a surface of the growthsubstrate a buffer layer used for subsequent growth of a luminescentepitaxial structure;

2) forming a semiconductor dielectric layer on the surface of the bufferlayer;

3) by means of a photolithography process, etching a plurality ofprotrusions arranged at intervals on the semiconductor dielectric layer,and exposing the buffer layer between the protrusions.

From the above, the invention provides a substrate used forIII-V-nitride growth and a manufacturing method thereof. Because thenovel patterned substrate uses a semiconductor dielectric layer as amask, the effect of the selective growth is apparent, and thus it mayenhance the quality of the epitaxial layer, reduce the dislocationdensity, improve the performance of the LED chip and enhance theinternal quantum efficiency of the LED. Besides, the invention choosesthe semiconductor dielectric layer with a relative small refractiveindex to manufacture the periodically arranged protrusion structure,which may enhance the reflection and scattering effects of the emittedlight by the LED, as well as improve the luminescent efficiency of theLED.

Moreover, it is not necessary for the novel patterned substrate to adoptthe two-step grown method to grow the LED epitaxial structure, butdirectly perform a high temperature growth, as a result, it may decreasethe growth time of the LED epitaxial structure and reduce the epitaxialcost.

The manufacturing method of the invention is simple, advantageous forreducing cost of manufacture, and suitable for use in industrialproduction. To be specific, since the process of the semiconductordielectric layer is a very common and conventional technology in thesemiconductor technology, the process of the semiconductor dielectriclayer is much easier than that of the sapphirine, the method is verycompatible with the LED chip technology, easy for mass production andthe preparation process window thereof is wider than that of aconventional PSS substrate, the photoetching and the product yield ishigh as well. The technology may increase capacity of the patternedsubstrate and reduce cost of the patterned substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 2 show schematic diagrams represented in step 1) of asubstrate used for the III-V-nitride growth of the invention.

FIG. 3 shows a schematic diagram represented in step 2) of amanufacturing method of the substrate used for the III-V-nitride growthof the invention.

FIGS. 4 to 7 show schematic diagrams represented in step 3) of themanufacturing method of the substrate used for the III-V-nitride growthof the invention.

DESCRIPTION OF COMPONENT REFERENCE SIGNS

101 growth substrate

102 buffer layer

103 semiconductor dielectric layer

104 photoresist layer

105 photoresist piece

106 bump-shaped photoresist piece

107 semiconductor dielectric protrusion

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As a preferable solution of the substrate used for the III-V-nitridegrowth of the invention, the material of the growth substrate is one ofsapphirine, SiC, Si and ZnO.

As a preferable solution of the substrate used for the III-V-nitridegrowth of the invention, the buffer layer has a thickness of 50-600angstroms, preferably 100-500 angstroms, more preferably 200-400angstroms. An excessively thin buffer layer cannot satisfy thenucleation requirement in the subsequent epitaxial growth, which causesthe reduce of the growth quality of the epitaxial layer; an excessivelythick buffer layer may cause an insufficient recrystallization of thebuffer layer in the subsequent annealing process, which further affectsthe quality of the epitaxial layer; an excessively thick buffer layermay also affect the luminescent efficiency of the LED prepared on thesubstrate.

As a preferable solution of the substrate used for the III-V-nitridegrowth of the invention, the buffer layer is any of amorphous orpolycrystalline materials of a hexagonal symmetrical structure crystalformed by anneal and recrystallization, and preferably selected from:Al_(x)Ga_(1-x)N prepared by a metal-organic chemical vapor depositionmethod with 0≦X≦0.5, preferably and a 0≦X≦0.2 and a preparationtemperature range of 450-700 ° C., preferably 500-600 ° C.; AlN preparedby the metal-organic chemical vapor deposition method with a preparationtemperature range of 700-1000° C.; an AlN layer prepared by a sputteringmethod with a (0001) crystal orientation; BN; or ZnO. The manufacturingmethod of the buffer layer is well-known by those skilled in the art,and is not further described herein.

Because the preparation temperature of the buffer layer is relative low,and the required thickness is relative small as well, it may effectivelyreduce the production cost while guaranteeing the nucleation growth ofthe subsequent luminescent epitaxial structure (especially the GaN basedluminescent epitaxial structure). As compared to the low temperatureAl_(x)Ga_(1-x)N layer, the preparation of the AlN layer by thesputtering method has the advantages of strong controllability ofthickness, relative high degree of crystallographic orientation, and isadvantageous for the nucleation growth of the luminescent epitaxialstructure (especially the GaN based luminescent epitaxial structure).

As a preferable solution of the substrate used for the III-V-nitridegrowth of the invention, the semiconductor dielectric protrusion is atleast one of SiO₂, SiN or SiON, and preferably SiO₂.

As a preferable solution of the substrate used for the III-V-nitridegrowth of the invention, the semiconductor dielectric protrusion has aheight of 0.2-3 μm, and preferably 0.5-2 μm.

As a preferable solution of the substrate used for the III-V-nitridegrowth of the invention, the plurality of semiconductor dielectricprotrusions are periodically arranged at intervals, the semiconductordielectric protrusion has a bottom width of 0.3-4 μm and an interval of0.1-2 μm. In principle, the smaller the bottom width of thesemiconductor dielectric protrusion is, the smaller the interval is.

As a preferable solution of the substrate used for the III-V-nitridegrowth of the invention, the semiconductor dielectric protrusion is asemiconductor dielectric bump-shaped protrusion, semiconductordielectric conoid-shaped protrusion or semiconductor dielectricpyramid-shaped protrusion. The bump-shaped protrusion with a relativeflat surface may effectively improve the growth quality of thesubsequent luminous epitaxial structure (especially the GaN basedluminescent epitaxial structure), and is therefore preferred.

As a preferable solution of the substrate used for the III-V-nitridegrowth of the invention, the protrusion has a bottom surface connectedwith the upper surface of the buffer layer, a shape of the bottomsurface is one of a polygon, triangle or circle or a combinationthereof.

As a preferable solution of the substrate used for the III-V-nitridegrowth of the invention, the protrusion further has a top surfaceparalleling to the bottom surface, the top surface is one of a polygon,triangle or circle or a combination thereof.

As a preferable solution of the substrate used for the III-V-nitridegrowth of the invention, the top surface has a same shape with thebottom surface but a smaller area than the bottom surface.

As a preferable solution of the substrate used for the III-V-nitridegrowth of the invention, the top surface has a different shape with thebottom surface and a smaller area than the bottom surface.

As a preferable solution of the manufacturing method of the substrateused for the III-V-nitride growth of the invention, the material of thegrowth substrate is one of the sapphirine, SiC, Si and ZnO.

As a preferable solution of the manufacturing method of the substrateused for the III-V-nitride growth of the invention, the buffer layer hasa thickness of 50-600 angstroms, preferably 100-500 angstroms, morepreferably 200-400 angstroms.

As a preferable solution of the manufacturing method of the substrateused for the III-V-nitride growth of the invention, the buffer layer isany of amorphous or polycrystalline materials of a hexagonal symmetricalstructure crystal formed by anneal and recrystallization, and morepreferably selected from: Al_(x)Ga_(1-x)N prepared by the metal-organicchemical vapor deposition method with 0≦X≦0.5, preferably 0≦X≦0.2 and apreparation temperature range of 450-700° C., preferably 500-600° C.;AlN prepared by the metal-organic chemical vapor deposition method witha preparation temperature range of 700-1000° C.; an AlN layer preparedby the sputtering method with a (0001) crystal orientation; BN; or ZnO.

As a preferable solution of the manufacturing method of the substrateused for the III-V-nitride growth of the invention, in step 2), a plasmaenhanced chemical vapor deposition (PECVD) method is adopted to form asemiconductor dielectric layer on the buffer layer, wherein thedielectric material is at least one of SiO₂, SiN or SiON, and preferablySiO₂. In a preferable solution, the SiO₂ semiconductor dielectric layeris grown by using SiH₄ and N₂O at a temperature range of 250-350° C. andunder the plasma reaction environment by adopting the PECVD method.

As a preferable solution of the manufacturing method of the substrateused for the III-V-nitride growth of the invention, the semiconductordielectric layer in step 2) has a thickness of 0.2-3 μm, and preferably0.5-2 μm.

As for the manufacturing method of the substrate used for theIII-V-nitride growth of the invention, etching the dielectric layer to aplurality of protrusions arranged at intervals in step 3) is a verycommon and conventional technology in the semiconductor process, and iswell-known by those skilled in the art, and thus is not furtherdescribed herein.

As a preferable solution of the manufacturing method of the substrateused for the III-V-nitride growth of the invention, the plurality ofsemiconductor dielectric protrusions are periodically arranged atintervals, the semiconductor dielectric protrusion has a bottom width of0.3-4 μm and an interval of 0.1-2 μm. In principle, the smaller thebottom width of the semiconductor dielectric protrusion is, the smallerthe interval is.

As a preferable solution of the manufacturing method of the substrateused for the III-V-nitride growth of the invention, the semiconductordielectric protrusion in step 3) is a semiconductor dielectricbump-shaped protrusion, semiconductor dielectric conoid-shapedprotrusion or semiconductor dielectric pyramid-shaped protrusion, andpreferably a semiconductor dielectric bump-shaped protrusion.

As a preferable solution of the manufacturing method of the substrateused for the III-V-nitride growth of the invention, the protrusion has abottom surface connected with the upper surface of the buffer layer, thebottom surface is one of a polygon, triangle or circle or a combinationthereof.

Further, the semiconductor dielectric protrusion is the semiconductordielectric bump-shaped protrusion, and the step 3) comprises steps of:

3-1) forming a photoresist layer on a surface of the semiconductordielectric layer, making the photoresist layer into a plurality ofphotoresist pieces arranged at intervals;

3-2) reflowing the plurality of photoresist pieces into a plurality ofbump-shaped photoresist pieces by using a heating-reflow process;

3-3) transferring the shape of each bump-shaped photoresist piece to thesemiconductor dielectric layer by using an inductively coupled plasmaetching method, to form a plurality of semiconductor dielectricbump-shaped protrusions and to expose the buffer layer between thesemiconductor dielectric bump-shaped protrusions for the subsequentgrowth of the GaN based luminescent epitaxial structure.

Preferably, in the step 3-1), the photoresist layer may be made into aplurality of photoresist pieces arranged at intervals by using theexposure process or nano-imprint process, and the exposure process maybe a stepper exposure or contact exposure.

EMBODIMENT

The embodiment modes of the present invention are described hereunderthrough specific examples, and persons skilled in the art may easilyunderstand other advantages and efficacies of the present invention fromthe contents disclosed in the present description. The present inventionmay be further implemented or applied through other different specificembodiment modes, and various modifications or amendments may also bemade to each of the details in the present description based ondifferent perspectives and applications without departing from thespirit of the present invention.

Please refer to FIG. 1 to FIG. 7. It is to be noted that the drawingsprovided in the present embodiment only explain the basic conception ofthe present invention in an illustrative manner, so the drawings onlydisplay the components relevant to the present invention rather thanbeing drawn according to the number, shape, size of the components andmanufacturing method, process window during actual implementation, theshape, number and scale of each component may be randomly changed duringits actual implementation, and the layout of the components thereofmight also be more complicated. In the embodiments, the involved processconditions may be reasonably changed in the effective window to achievethe effect disclosed in the invention.

Embodiment 1

As shown in FIGS. 1 to 7, the embodiment provides a substrate used forGaN growth, and the manufacturing method thereof comprises the followingsteps of:

1. As shown in FIG. 1, in the embodiment, the growth substrate 101 is acommercially available flat type sapphirine substrate, wherein a surfacethereof has a crystal orientation of (0001), and has an atomisticflatness. In the embodiment, a cleaning-free substrate is adoptedwithout extra cleaning processes and can be used directly. The abovesubstrate is placed on a graphite tray with a SiC protection layer andis sent to a MOCVD (metal organic chemical vapor phase depositionmethod) reaction chamber; the above substrate is heated to 1100° C.under an atmosphere of hydrogen, and kept for 10 minutes; after that,the temperature of the substrate is reduced to 550° C., the chamber isintroduced with ammonia gas, trimethylaluminium (TMAL) and trimethylgallium (TMGa) at the same time, wherein a normal flow rate of theammonia gas is 56 L/minute, molar flow rates of the TMAL and TMGa are3.25×10-5 and 2.47×10-4 mol/minute, respectively, a pressure of thereaction chamber is 500 torr, and the introduction time is 215 seconds.As shown in FIG. 2, the Al_(x)Ga_(1-X)N buffer layer, with a thicknessof 300 angstroms, is formed on the growth substrate 101 under the aboveconditions, wherein x=0.2.

2. As shown in FIG. 3, after the growth of the buffer layer 102, a SiO₂layer 103 with a thickness of 1 μm is formed on the buffer layer 102 byusing the PECVD (plasma enhanced chemical vapor deposition) method. ThePECVD reaction chamber has a temperature of 350° C. and a pressure of 1torr (a standard atmospheric pressure is 760 torr), flow rates of theSiH₄ and N₂O are 10 sccm and 300 sccm, respectively, radio frequencypower is 30 W.

3. Formation of the medium layer pattern. As shown in FIGS. 4 to 7, theformed pattern is formed by periodically and spatially arranged SiO₂protrusions, with an arrangement manner of hexagonal close-packedstructure and a period of 3 μm, the SiO₂ protrusion has a bottom widthof 2 μm and an interval of 1 μm.

To be specific, the step 3) comprises the following steps of:

As shown in FIGS. 4 and 5, firstly performing step 3-1), wherein asurface of the SiO₂ layer 103 is coated with a photoresist layer 104 of1 μm, which is made into a photoresist cylinder 105 of a hexagonalclose-packed arrangement manner by using an exposure process, thehexagonal close-packed structure has a period of 3 μm, the photoresistcylinder has a diameter of 2 μm and an interval of 1 μm.

As shown in FIG. 6, then performing step 3-2), wherein the plurality ofphotoresist cylinders are reflown into a half ball by using aheating-reflow process, wherein a reflux temperature thereof is 130° C.,and a reflux time thereof is 120 seconds.

After that, as shown in FIG. 7, performing step 3-3): the half ballshaped photoresist patterns are transferred to the SiO₂ layer 103 byusing an inductively coupled plasma (ICP) etching method, to form aplurality of SiO₂ bump-shape protrusions and expose the buffer layer 102between the SiO₂ bump-shape protrusions, for the following epitaxialgrowth of the GaN epitaxial material. Processing conditions of the aboveICP etching method is that: an etching gas is CHF₃ (fluoroform), and anormal flow rate thereof is 50 ml/min; the ICP has an upper electrodepower of 1000 w and a lower electrode power of 50 w.

4. Finally, use acetone to clean residual photoresist on the SiO₂surface, and use diluted hydrochloric acid to clean other contaminantson the surfaces of the SiO₂ protrusions and the exposed surface of thebuffer layer for further epitaxial growth of the GaN.

By using the same MOCVD equipment, the GaN epitaxial layer with athickness of 6 microns is respectively epitaxially grown on a patternedsapphirine substrate (PSS) and the novel patterned substrate prepared bythe above steps of the invention. The specific growth conditions of theMOCVD is that: the growth temperature is 1050 degree, the heating andannealing time from the room temperature to the growth temperature is 15minutes; the pressure of the reaction chamber is 500 torr, the normalflow rate of the ammonia gas is 56 L/min; the molar flow rate of theTMGa is 1.5e-3 mol/min, and the growth time is 150 minutes.

A XRD (X-ray double-crystal diffraction) spectrum is used tocharacterize the crystalline epitaxial layer quality, the smaller thehalf-width of the XRD spectrum is, the smaller the dislocation densityof the crystalline epitaxial layer represents, and the higher thecrystalline quality is. The testing results indicate that, thehalf-widths of the XRD (002) and (102) diffraction peaks of the GaNepitaxial layer grown on the conventional PSS substrate are 280 arcseconds and 302 arc seconds respectively, while the half-widths of theXRD (002) and (102) diffraction peaks of the GaN epitaxial layer grownon the prepared novel patterned substrate of the invention are 243 arcseconds and 258 arc seconds respectively. From the above experiments, itis apparent that the GaN epitaxial layer grown on the prepared novelpatterned substrate by the above steps has better quality than the GaNepitaxial layer grown on the conventional PSS substrate.

Moreover, a measurement of the luminescent efficiency is performed onthe LED devices grown on the two substrates. As compared to theconventional PSS substrate, the luminous efficiency of the LED preparedon the substrate of the invention is greatly improved. Average luminousflux of the packaged 3528 LED chip on the conventional PSS substrate is18.30 lm; while the average luminous flux of the LED chip prepared onthe substrate of the invention is 19.23 lm, the luminous efficiencythereof is improved by 5% or more.

Embodiment 2

As shown in FIGS. 1 to 7, the embodiment provides a manufacturing methodof the substrate used for the GaN growth, and the basic steps are sameas that in the embodiment 1, except that in the second step: thesemiconductor medium layer 103 is a SiN layer prepared by using a PECVDmethod, wherein raw material for growing the SiN layer is NH₃ (ammoniagas) and SiH₄ (silane), the growth temperature is 400° C., the flow rateof SiH₄ is 20 sccm, the flow rate of NH₃ is 17 sccm, the flow rate of N₂is 980 sccm, and the pressure is 0.8 torr.

By using the same MOCVD equipment, a GaN epitaxial layer with athickness of 6 microns is respectively epitaxially grown on theconventional PSS substrate and the novel patterned substrate prepared bythe above steps by using substantially same conditions. In the aboveexperiments, the half-widths of the XRD (002) and (102) diffractionpeaks of the GaN epitaxial layer grown on the conventional PSS substrateare 280 arc seconds and 302 arc seconds respectively, while thehalf-widths of the XRD (002) and (102) diffraction peaks of the GaNepitaxial layer grown on the prepared novel patterned substrate of theinvention are 270 arc seconds and 283 arc seconds respectively. From theabove experiments, it is apparent that the prepared novel patternedsubstrate in the invention has further advantage over the conventionalPSS substrate.

Embodiment 3

As shown in FIGS. 1 to 6, the embodiment provides a manufacturing methodof the substrate used for the GaN growth, with substantially same stepsas in embodiment 1, wherein, the buffer layer 102 is an AlN layer with athickness of 200 angstroms prepared by using the physical vapordeposition (PVD) method, an adopted target is Al target, sputtering gasis N₂, a substrate temperature is 600° C., and a sputtering power is 600W. The obtained AlN is a columnar polycrystal with a prominent crystalorientation arrangement of (0001).

By using the same MOCVD equipment, a GaN epitaxial layer with athickness 6 microns is respectively epitaxially grown on theconventional PSS substrate and the novel patterned substrate prepared bythe above steps by using substantially same conditions. In the aboveexperiments, the half-widths of the XRD (002) and (102) diffractionpeaks of the GaN epitaxial layer grown on the conventional PSS substrateare 280 arc seconds and 302 arc seconds respectively, while thehalf-widths of the XRD (002) and (102) diffraction peaks of the GaNepitaxial layer grown on the prepared novel patterned substrate of theinvention are 237 arc seconds and 253 arc seconds respectively. From theabove experiments, it is apparent that the prepared novel patternedsubstrate in the invention has further advantage over the conventionalPSS substrate.

The abovementioned embodiments only illustratively describe theprinciple and efficacy of the present invention, rather than being usedto limit the present invention. Any person skilled in the art may modifyor amend the abovementioned embodiments without departing from thespirit and scope of the present invention. Thus, all equivalentmodifications or amendments accomplished by persons having commonknowledge in the technical field concerned without departing from thespirit and technical thoughts revealed by the present invention shallstill be covered by the claims of the present invention.

1. A substrate used for III-V-nitride growth at least comprising: agrowth substrate; a buffer layer used for growing a subsequentluminescent epitaxial structure, wherein a lower surface of the bufferlayer is combined with a surface of the growth substrate; and aplurality of semiconductor dielectric protrusions arranged at intervalson an upper surface of the buffer layer, bottom surfaces of theprotrusions are combined with the upper surface of the buffer layer, andthe buffer layer is exposed between protrusions.
 2. The substrate usedfor III-V-nitride growth as in claim 1, wherein: material of the growthsubstrate is one of a sapphirine, SiC, Si and ZnO.
 3. The substrate usedfor III-V-nitride growth as in claim 1, wherein: the buffer layer has athickness of 50-600 angstroms.
 4. The substrate used for III-V-nitridegrowth as in claim 1, wherein: the buffer layer is amorphous orpolycrystalline material selected from: Al_(x)Ga_(1-x)N prepared by ametal-organic chemical vapor deposition method with 00.5 and apreparation temperature range of 450-700° C.; AN prepared by ametal-organic chemical vapor deposition method with a preparationtemperature range of 700-1000° C.; an AlN layer prepared by a sputteringmethod with a (0001) crystal orientation; BN; or ZnO.
 5. The substrateused for III-V-nitride growth as in claim 1, wherein: the protrusion isat least one of SiO₂, SiN or SiON.
 6. The substrate used forIII-V-nitride growth as in claim 1, wherein: the protrusion has a heightof 0.2-3 μm.
 7. The substrate used for III-V-nitride growth as in claim1, wherein: the plurality of protrusions are periodically arranged atintervals, the protrusion has a width of 0.3-4 μm and an interval of0.1-2 μm.
 8. The substrate used for III-V-nitride growth as in claim 1,wherein: the semiconductor dielectric protrusion is a semiconductordielectric bump-shaped protrusion, semiconductor dielectricconoid-shaped protrusion or semiconductor dielectric pyramid-shapedprotrusion.
 9. The substrate used for III-V-nitride growth as in claim1, wherein: the protrusion has a bottom surface connected with the uppersurface of the buffer layer, a shape of the bottom surface is one of apolygon, triangle or circle or a combination thereof.
 10. The substrateused for III-V-nitride growth as in claim 9, wherein: the protrusionfurther has a top surface paralleling to the bottom surface, the topsurface is one of a polygon, triangle or circle or a combinationthereof.
 11. The substrate used for III-V-nitride growth as in claim 9,the top surface has a same shape with the bottom surface but a smallerarea than the bottom surface.
 12. The substrate used for III-V-nitridegrowth as in claim 9, the top surface has a different shape with thebottom surface and a smaller area than the bottom surface.
 13. Amanufacturing method for a substrate used for III-V-nitride growth, atleast comprising steps of: 1) providing a growth substrate, and formingon a surface of the growth substrate a buffer layer used for subsequentgrowth of a luminescent epitaxial structure; 2) forming a semiconductordielectric layer on the surface of the buffer layer; 3) by means of aphotolithography process, etching a plurality of protrusions arranged atintervals on the dielectric layer, and exposing the buffer layer betweenthe protrusions.
 14. The manufacturing method for the substrate used forIII-V-nitride growth as in claim 13, wherein: a material of the growthsubstrate is one of a sapphirine, SiC, Si and ZnO.
 15. The manufacturingmethod for the substrate used for III-V-nitride growth as in claim 13,wherein: the buffer layer has a thickness of 50-600 angstroms.
 16. Themanufacturing method for the substrate used for III-V-nitride growth asin claim 13, wherein: the buffer layer is amorphous or polycrystallinematerial selected from at least one of: Al_(x)Ga_(1-x)N prepared by ametal-organic chemical vapor deposition method with 00.5 and apreparation temperature range of 450-700° C.; AN prepared by ametal-organic chemical vapor deposition method with a preparationtemperature range of 700-1000° C.; an AlN layer prepared by a sputteringmethod with a (0001) crystal orientation; BN; or ZnO.
 17. Themanufacturing method for the substrate used for III-V-nitride growth asin claim 13, wherein: in step 2), a plasma enhanced chemical vapordeposition method is adopted to form a dielectric layer on the bufferlayer, the dielectric material is at least one of SiO₂, SiN or SiON. 18.The manufacturing method for the substrate used for III-V-nitride growthas in claim 13, wherein: the dielectric layer in step 2) has a thicknessof 0.2-3 μm.
 19. The manufacturing method for the substrate used forIII-V-nitride growth as in claim 13, wherein: the plurality ofprotrusions are periodically arranged at intervals, the protrusion has awidth of 0.3-4 μm and an interval of 0.1-2 μm.
 20. The manufacturingmethod for the substrate used for III-V-nitride growth as in claim 13,wherein: the protrusion in step 3) is a bump-shaped protrusion, aconoid-shaped protrusion or a pyramid-shaped protrusion.
 21. Themanufacturing method for the substrate used for III-V-nitride growth asin claim 20, wherein: the protrusion has a bottom surface connected withthe upper surface of the buffer layer, the bottom surface is one of apolygon, triangle or circle or a combination thereof.
 22. Themanufacturing method for the substrate used for III-V-nitride growth asin claim 13, wherein: the protrusion is semiconductor dielectricbump-shaped protrusion, and the step 3) comprises steps of: 3-1) forminga photoresist layer on a surface of the semiconductor medium layer,making the photoresist layer into a plurality of photoresist pieces byan exposure process or nano-imprint process; 3-2) reflowing theplurality of photoresist pieces into a plurality of bump-shapedphotoresist pieces by using a heating-reflow process; 3-3) transferringthe shape of the bump-shaped photoresist piece to the semiconductordielectric layer by using an inductively coupled plasma etching method,to form a plurality of semiconductor dielectric bump-shaped protrusionsand to expose the buffer layer between SiO₂ bump-shape protrusions forthe growth of a subsequent luminescent epitaxial structure.